In the present text, the term “processor unit” refers to any machine adapted to execute one or more distinct tasks automatically. It can be a hard-wired processor unit. It is preferably a programmable processor unit including a processor (microprocessor, microcontroller, etc.) programmed to execute one or more distinct tasks automatically. The processor unit can be programmable machine, such as a microcomputer, for example, a peripheral of a machine, a daughter card mounted on a backplane mother card, etc. This list is not exhaustive.
At present, in electronic architectures comprising a plurality of processor units interconnected by a communication bus, each processor unit is identified on the bus by a physical address that is specific to it. Existing communication protocols enable a first processor unit (referred to hereinafter as the sender unit) to communicate with a second processor unit (referred to hereinafter as the target unit). Accordingly, when the sender unit sends a message to the target unit, for example to trigger the execution of a predefined task by the target unit, the sender unit sends the address of the target unit on the bus. Each processor unit is able to decode an address sent on the bus and if a target unit recognizes its own address it loads the associated message into local memory and executes the task for which it is programmed. The target unit and the sender unit generally have similar fixed size address and data buses.
With existing architectures and communication protocols of the above types, it is difficult to produce a multitasking system in which a plurality of processor units execute the same task (or function) in parallel, because this kind of parallel working of the processor units necessitates complex management of processor unit addressing.